The present invention relates to semiconductor device assemblies, and more particularly, to techniques and apparatuses for analyzing and debugging circuitry associated with an integrated circuit.
In recent years, the semiconductor industry has realized tremendous advances in technology which have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of hundreds of MIPS (millions of instructions per second), to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high-density and high functionality in semiconductor devices has been the demand for increased numbers of external electrical connections to be present on the exterior of the die and on the exterior of the semiconductor packages which receive the die, for connecting the packaged device to external systems, such as a printed circuit board.
To increase the number of pad sites available for a die, different chip packaging techniques have been used. One of many related package types is called controlled collapse chip connection or flip chip packaging. This technology uses the bonding pads and metal (solder) bumps. To increase the density of the inputs and outputs, the bonding pads are moved to the site nearest the transistors and other circuit devices formed in the die. As a result, the electrical path to the pad is shorter. Electrical connection to the package is made when the die is flipped over the package with corresponding bonding pads. Each bump connects to a corresponding package inner lead. The resulting packages have a lower profile, a lower electrical resistance and a shortened electrical path. The output terminals of the package may be ball-shaped conductive-bump contacts (usually solder, or other similar conductive material) are typically disposed in a rectangular array. These packages are occasionally referred to as xe2x80x9cBall Grid Arrayxe2x80x9d (BGA). Alternatively, the output terminals of the package may be pins, and such a package is commonly known as pin grid array (PGA).
For BGA, PGA and other types of packages, once the die is attached to the package, the backside portion of the die remains exposed. The transistors and other circuitry are generally formed in a very thin epitaxially grown silicon layer on a single crystal silicon wafer of which the die is singulated from. The side of the die including the epitaxial layer containing the transistors, and the other active circuitry, is often referred to as the circuit side of the die or front side of the die. The circuit side of the die is positioned very near the package. The circuit side opposes the backside of the die. Between the backside and the circuit side of the die is single crystalline silicon. The positioning of the circuit side provides many of the advantages of the flip chip.
In some instances the orientation of the die with the circuit side face down on a substrate may be a disadvantage or present new challenges. For example, when a circuit fails or when it is necessary to modify a particular chip, access to the transistors and circuitry near the circuit side is typically obtained only from the backside of the chip. This is challenging since the transistors are in a very thin layer (about 10 micrometers) of silicon buried under the bulk silicon (greater than 500 micrometers). Thus, the circuit side of the flip chip die is not visible or accessible for viewing using optical or scanning electron microscopy.
Techniques have been developed to access the circuit even though the circuit of the integrated circuit (IC) is buried under the bulk silicon. For example, infrared (IR) microscopy is capable of imaging the circuit because silicon is relatively transparent in these wavelengths of the radiation. However, because of the absorption losses of IR radiation in silicon, it is generally required to thin the die to less than 100 microns in order to view the circuit using IR microscopy. On a die that is 725 microns thick, this means removing at least 625 microns of silicon before IR microscopy can be used.
Thinning the die for failure analysis of a flip chip bonded IC is usually accomplished in two or three steps. The backside of the die is first thinned across the whole surface. This is also referred to as global thinning. Global thinning is done to allow viewing of the active circuit from the backside of the die using IR microscopy. Mechanical polishing is one method for global thinning. Using IR microscopy, an area is identified for accessing to a particular area of the circuit. Local thinning techniques such as laser microchemical etching are used to thin the silicon area to a level that is thinner than the die size. One method for laser microchemical etching of silicon is accomplished by focusing a laser beam on the backside of the silicon surface to cause local melting of silicon in the presence of chlorine gas. The molten silicon reacts very rapidly with chlorine and forms silicon tetrachloride gas, which leaves the molten (reaction) zone. A specific example silicon-removal process uses the 9850 SiliconEtcher(trademark) tool by Revise, Inc. (Burlington, Mass.). This laser process is suitable for both local and global thinning by scanning the laser over a part of, or the whole, die surface.
During failure analysis, or for design debug, it is sometimes helpful to access probe points on the circuit side or front side of the die. Milling through the die to access the node, or milling to the node and subsequently depositing a metal to electrically access the node generally does this. For design debug, it is desirable to have the capability of obtaining a waveform via probe points. For these reasons, it is necessary to have a method and apparatus which will provide for obtaining a waveform on the circuit side of the die. It is also necessary to be able to obtain a waveform without damaging the device or otherwise jeopardizing further device analysis.
Accordingly, flip chip technology would benefit from a method and apparatus for readily accessing a probe point for waveform acquisition within a semiconductor device. This is helpful for reducing any guesswork as to the location of the circuitry while the backside of a die is being removed, improving the ability to maintain the integrity of the device. If this guesswork is reduced or eliminated, failure analysis and debugging of the circuitry associated with a particular integrated circuit is improved. Furthermore, when the probe point is easily found, acquiring a waveform can be accomplished in less time.
The method and apparatus described herein is directed to manufacturing and post-manufacturing testing of a semiconductor device. In an example embodiment, a semiconductor device manufacture includes forming a trench in a portion of the backside of a semiconductor device having a circuit side and a backside. At least a portion of the trench is filled with conductive material to form a probe point that extends into the backside. After the semiconductor device is manufactured, the semiconductor device is tested by milling the backside of the semiconductor device to access the probe point. Using a test fixture, the semiconductor device is powered and energy coupled from the probe point is acquired to obtain a voltage waveform at the node to which the probe point is coupled. In a more specific approach, e-beam microscopy is used to detect the waveform at the probe point. In certain implementations, the probe point is capacitively coupled to the node, and in other implementations, the probe point is directly connected to the target node.
In another implementation, the present invention is directed to voltage waveform acquisition from a first target node by charging a second target node via its associated probe point. An electron beam detector is used to acquire a voltage waveform from the probe point that is coupled to another target node. In this implementation, the target nodes are selected such that a certain response from the first target node is predicted in response to an applied charge at the second target node.
The above summary is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and the detailed description which follow more particularly exemplify these embodiments.